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SAN JOSE, Calif.--(BUSINESS WIRE)--June 11, 2001-- Tensilica® Inc., the leading supplier of extensible, configurable processor semiconductor intellectual property (SIP), today unveiled its fourth-generation of the Xtensa(TM) processor technology. The Xtensa IV technology features advanced capabilities to facilitate the integration of multiple processors within System-On-Chip (SOC) implementations. In addition, the company has introduced a host of new configuration options and development tools that will allow system designers to further optimize the Xtensa architecture for specific applications.

``Many system designers acknowledge that the integration of multiple processors on SOCs is critical to next-generation embedded systems, but few processor vendors provide this capability beyond the simplest case: one CPU and one DSP,'' said Chris Rowen, president and CEO of Tensilica Inc. ``The Xtensa processor's flexibility has already enabled many Tensilica customers to design SOC devices with three or more Xtensa cores. The Xtensa IV core is even more multiprocessor-friendly, providing a development environment that enables designers to reduce time-to-market and optimize the performance of SOCs with multiple Xtensa processor cores.''

A New Definition of Multiprocessing

The traditional view of multiprocessing in general purpose computing systems has been a cluster of two, four, or eight or more identical processors coupled via traditional bus structures. Terms such as symmetric multiprocessing (SMP) or massively parallel computing have been used to describe these systems. By contrast, in consumer and communications SOCs, designers are deploying a combination of uniquely configured task engines -- many of which are tightly coupled to each other -- in dataflow or ``dataplane'' functions, often as an alternative to implementing fixed-function RTL logic.

``Tensilica's foray into CMP (chip-level multiprocessing) through its Xtensa IV architectural enhancements shows where SOC development is headed,'' said Steve Leibson, VP, Editorial Director, and Chief Analyst at MicroDesign Resources. ``The number of transistors available on commercially viable silicon is quickly reaching the point where it makes tremendous sense to place multiple processors on one die. A configurable core that can be optimized for a variety of tasks, like Xtensa IV, makes a tremendous amount of sense in these applications.''

Hughes Network Systems Chooses Xtensa for Multiprocessing SOC

Hughes Network Systems (HNS) recently chose the Xtensa processor for Spaceway(TM), the next generation satellite-based broadband network for consumers and enterprises. According to HNS, Spaceway's system architecture required a System on Chip containing multiple unique processors, each precisely tuned to an assigned function. ``After an extremely thorough evaluation of processors from several industry-leading companies, it was clear to us that Tensilica's Xtensa core provided the performance, time-to-market, and verification specifications that we required,'' said Dan Fraley, Hughes Networks Systems' senior vice president of engineering.

HNS will use numerous uniquely configured Xtensa processors in their SOCs for Spaceway. These will provide all of the processing requirements including high speed real-time data stream management plus running a leading RTOS on an Xtensa core configured as a high-end control processor.

Key Enhancements to the Xtensa Architecture

The Xtensa IV processor is the newest generation of the company's proven configurable and extensible microprocessor architecture. The Xtensa architecture provides a superior alternative to traditional rigid processors and simple configurable processor architectures that limit designers to the performance of either a ``one size fits all'' general-purpose MPU or a limited number of configurations. Tensilica's powerful, integrated hardware and software development environment offers thousands of configuration options and an unlimited range of customer-specific extensions which enable designers to carefully tune the processor for specific functionality. With an easy-to-use graphical interface, designers can take advantage of Tensilica's processor generator to create customized MPU solutions with specialized functions and instructions. Because these instructions are recognized as ``native'' by software, developers can simultaneously tune both application software and processor hardware to meet specific speed, power and feature goals.

The Xtensa IV core delivers all of the unique features of the Xtensa architecture and has been enhanced to also include the following:

System Simulation and Implementation

• New System Modeling API: Tensilica has developed a new system modeling and simulation application programming interface (API) and function library. The API reduces overall design time by allowing rapid construction of C simulations of one or more Xtensa processors, on-chip memory, buses, bus bridges and other peripherals. As a result, designers can now explore topologies and load balancing for multiple processor systems and get detailed performance simulation with rapid iteration cycles.
• C-Callable Instruction Set Simulator: Xtensa's Instruction Set Simulator has been enhanced to be C/C++-callable in multiprocessor system simulations. By integrating a configured instruction set simulator for each core produced by the Xtensa generator into an existing C simulation environment, Tensilica customers can rapidly create and iterate a C-level model of a multiple processor configuration running real compiled C-code.
• Xtensa Local Memory Interface (XLMI): Xtensa IV offers a new high-speed local memory interface that can be used to optimize the performance of SOCs with multiple processors. The XLMI port can be used to tightly couple Xtensa processors used in dataflow instantiations, as well as integrate existing hardwired, high-performance complex state machine logic into the Xtensa processor's memory space. The XLMI interface can be configured up to a full 128-bit width, delivering up to 3.2GB/s (peak) low-latency memory bandwidth. The XLMI interface is supported by system modeling capabilities both in software, through Xtensa's Instruction Set Simulator, and in hardware, through bus functional models.
• Robust Debugging Environment: Tensilica offers a robust, multiprocessing debugging environment that enables users to seamlessly transition from software simulation to actual hardware debugging using a consistent GNU-based software development tool chain. Xtensa IV adds selective hardware debug breakpoint capability for multiprocessing SOCs. Through a single daisy-chained, on-chip debug port, users can monitor and debug software using a single host with selective conditional breakpoints. On chip user-defined trace buffer functionality can also be added to the SOC using Xtensa's trace port for complete and comprehensive multiprocessing debugging solution.

Software Development Environment

     Tensilica, Inc.
     Stephen Roddy, 408/566-1748 (Reader)
     roddy@tensilica.com
     Kim Alfaro, 408/327-7343 (Editorial)
     kim@tensilica.com
          or
     Tanis Communications
     Joany Draeger, 650/365-3395 (Editorial)
     joany@taniscomm.com